Technical Field
The present invention relates to a package substrate for IC package, the package substrate comprises a redistribution layer (RDL) with a plurality of metal pillar configured on high density side, i.e. chip side, for connecting to an IC chip. The height of the metal pillar defines a space between the IC chip and the package substrate. An underfill shall be filled in the space to ensure package reliability.
Description of Related Art
FIG. 1A shows a prior art substrate for IC package
FIG. 1A shows a prior art substrate for IC package disclosed in US2014/0102777A1 which has an embedded silicon interposer 20. The silicon interposer 20 has four lateral sides 206. A molding compound 22 wraps the silicon interposer 20 around the four lateral sides 206. A plurality of via metal 200 is made through the silicon interposer 20. An insulation liner 201 is made between the through via 200 and the silicon interposer 20 for an electrical insulation there-between. A top redistribution layer 21 is made on top of the silicon interposer 20 with a plurality of metal pad 210 exposed on top. The plurality of metal pad 210 on top is provided for accommodating an IC chip (not shown) to mount. A circuit built-up layer 25 is made on bottom of the silicon interposer 20 with a plurality of metal pad 220 configured on bottom. A plurality of solder ball 24 is configured and each solder ball 24 is configured on bottom of a corresponding bottom metal pad 220.
FIG. 1B shows a reversed view of FIG. 1A. FIG. 1B is made to present the prior art of FIG. 1A in a position similar to a package substrate of the present invention to facilitate a comparison there between. FIG. 1B shows an up-down view of FIG. 1A. The top solder ball 24 is configured for mounting the package substrate onto a mother board (not shown). The bottom metal pad 210 is configured for a chip or chips to mount.